Implement optimized movemasks for NEON #1236
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While the scalar post-processing required to obtain one bit per lane makes this more expensive than directly supporting variable-sized bit groups (as done in Zstandard[^1]), the result is still an improvement over the current lane-by-lane algorithm. [^1]: See facebook/zstd#3139, namely `ZSTD_row_matchMaskGroupWidth`.
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I've suggested an improvement of the 64 bit version there: https://godbolt.org/z/b7henc933 |
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Applied, thank you for the suggestion. I will fix the GCC build in a moment. |
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| template <class A, class T, detail::enable_sized_t<T, 1> = 0> | ||
| XSIMD_INLINE uint64_t mask(batch_bool<T, A> const& self, requires_arch<neon>) noexcept | ||
| { | ||
| uint8x16_t inner = self; |
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You should probably use the method described in https://github.com/DLTcollab/sse2neon/blob/ade5552a32852422e4f34f0beaa51790ef9f4171/sse2neon.h#L5574.
It performs the reduction in parallel and that seems more efficient!
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While the scalar post-processing required to obtain one bit per lane
makes this more expensive than directly supporting variable-sized bit
groups (as done in Zstandard1), the result is still an improvement
over the current lane-by-lane algorithm.
To reduce duplication,
XSIMD_LITTLE_ENDIANis moved frommath/xsimd_rem_pio2.hpptoconfig/xsimd_config.hpp, and will now beavailable outside the defining header.
Footnotes
See [lazy] Optimize ZSTD_row_getMatchMask for levels 8-10 for ARM facebook/zstd#3139, namely
ZSTD_row_matchMaskGroupWidth. ↩