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@taiki-e taiki-e commented Jan 7, 2026

From kernel docs: https://docs.kernel.org/arch/riscv/vector.html#vector-register-state-across-system-calls

3. Vector Register State Across System Calls

As indicated by version 1.0 of the V extension [1], vector registers are clobbered by system calls.

1: https://github.com/riscv/riscv-v-spec/blob/master/calling-convention.adoc

And the linked docs says:

Executing a system call causes all caller-saved vector registers (v0-v31, vl, vtype) and vstart to become unspecified.

See also this glibc bugfix: https://patchwork.sourceware.org/project/glibc/patch/[email protected]/
(Probably musl (riscv64, riscv32) also has the same bug. cc @Amanieu @kraj as target maintainers of corresponding Rust targets)

Unlike the above glibc patch which clobbers them depending on whether the vector ISA is enabled, this patch always clobbers them. (cfg(target_feature = “vector”) does not work except on nightly because the vector target feature is unstable. And, in Rust, always marking them as clobbered works fine (as clobber_abi does).

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