diff --git a/pyEDAA/ProjectModel/Xilinx/Vivado.py b/pyEDAA/ProjectModel/Xilinx/Vivado.py
index 4ed5d2e1..e2144199 100644
--- a/pyEDAA/ProjectModel/Xilinx/Vivado.py
+++ b/pyEDAA/ProjectModel/Xilinx/Vivado.py
@@ -149,7 +149,8 @@ def _ParseFile(self, fileNode, fileset):
 		else:
 			self._ParseDefaultFile(fileNode, filePath, fileset)
 
-	def _ParseVHDLFile(self, fileNode, path, fileset):
+	@staticmethod
+	def _ParseVHDLFile(fileNode, path, fileset):
 		vhdlFile = VHDLSourceFile(path)
 		fileset.AddFile(vhdlFile)
 		usedInAttr = vhdlFile[UsedInAttribute]
@@ -169,19 +170,24 @@ def _ParseVHDLFile(self, fileNode, path, fileset):
 						elif fileAttribute.getAttribute("Val") == "UsedIn":
 							usedInAttr.append(fileAttribute.getAttribute("Val"))
 
-	def _ParseDefaultFile(self, _, path, fileset):
+	@staticmethod
+	def _ParseDefaultFile(_, path, fileset):
 		File(path, fileSet=fileset)
 
-	def _ParseXDCFile(self, _, path, fileset):
+	@staticmethod
+	def _ParseXDCFile(_, path, fileset):
 		XDCConstraintFile(path, fileSet=fileset)
 
-	def _ParseVerilogFile(self, _, path, fileset):
+	@staticmethod
+	def _ParseVerilogFile(_, path, fileset):
 		VerilogSourceFile(path, fileSet=fileset)
 
-	def _ParseXCIFile(self, _, path, fileset):
+	@staticmethod
+	def _ParseXCIFile(_, path, fileset):
 		IPCoreInstantiationFile(path, fileSet=fileset)
 
-	def _ParseFileSetConfig(self, fileNode, fileset):
+	@staticmethod
+	def _ParseFileSetConfig(fileNode, fileset):
 		for option in fileNode.childNodes:
 			if option.nodeType == Node.ELEMENT_NODE and option.tagName == "Option":
 				if option.getAttribute("Name") == "TopModule":
diff --git a/tests/unit/Design.py b/tests/unit/Design.py
index 97b7975c..6200d847 100644
--- a/tests/unit/Design.py
+++ b/tests/unit/Design.py
@@ -140,7 +140,8 @@ def test_Files(self):
 
 
 class Validate(TestCase):
-	def test_Design(self):
+	@staticmethod
+	def test_Design():
 		project = Project("project", rootDirectory=Path("tests/project"))
 		design = Design("design", directory=Path("designA"), project=project)
 
diff --git a/tests/unit/File.py b/tests/unit/File.py
index 21bfdd07..abc3d6b9 100644
--- a/tests/unit/File.py
+++ b/tests/unit/File.py
@@ -146,7 +146,8 @@ def test_ResolveDirectory(self):
 
 
 class Validate(TestCase):
-	def test_File(self):
+	@staticmethod
+	def test_File():
 		project = Project("project", rootDirectory=Path("tests/project"))
 		design = Design("design", directory=Path("designA"), project=project)
 		fileSet = FileSet("fileset", design=design)
diff --git a/tests/unit/FileSet.py b/tests/unit/FileSet.py
index f378c8bd..c36a1230 100644
--- a/tests/unit/FileSet.py
+++ b/tests/unit/FileSet.py
@@ -232,7 +232,8 @@ def test_SourceFile(self):
 
 
 class Validate(TestCase):
-	def test_FileSet(self):
+	@staticmethod
+	def test_FileSet():
 		project = Project("project", rootDirectory=Path("tests/project"))
 		design = Design("design", directory=Path("designA"), project=project)
 		fileSet = FileSet("fileset", design=design)
diff --git a/tests/unit/Files.py b/tests/unit/Files.py
index 616f32fd..0b6f7374 100644
--- a/tests/unit/Files.py
+++ b/tests/unit/Files.py
@@ -96,7 +96,8 @@ def test_GetVersionFromFileSet(self):
 
 		self.assertEqual(vhdlVersion, file.VHDLVersion)
 
-	def test_Validate(self):
+	@staticmethod
+	def test_Validate():
 		project = Project("project", rootDirectory=Path("tests/project"), vhdlVersion=VHDLVersion.VHDL2019)
 		design = Design("design", directory=Path("designA"), project=project)
 		vhdlLibrary = VHDLLibrary("library", design=design)
diff --git a/tests/unit/Project.py b/tests/unit/Project.py
index a2c8e263..1c2a5814 100644
--- a/tests/unit/Project.py
+++ b/tests/unit/Project.py
@@ -109,7 +109,8 @@ def test_ResolveDirectory(self):
 
 
 class Validate(TestCase):
-	def test_Project(self):
+	@staticmethod
+	def test_Project():
 		project = Project("project", rootDirectory=Path("tests/project"))
 
 		project.Validate()