From 961f3ef8a491dbf48eabc77ae7b9e58e0687f4bd Mon Sep 17 00:00:00 2001 From: Matt Borgerson Date: Mon, 2 Feb 2026 15:47:48 -0700 Subject: [PATCH] Add updates from Ghidra 12.0.2 --- docs/guide.rst | 4 ++-- docs/index.rst | 2 +- pypcode/processors/AARCH64/data/languages/AARCH64base.sinc | 2 +- pypcode/processors/ARM/data/languages/ARMinstructions.sinc | 7 ++++--- pypcode/processors/PowerPC/data/languages/ppc_vle.sinc | 2 +- scripts/sleigh_download.sh | 2 +- 6 files changed, 10 insertions(+), 9 deletions(-) diff --git a/docs/guide.rst b/docs/guide.rst index 43fb747..1e71c6f 100644 --- a/docs/guide.rst +++ b/docs/guide.rst @@ -99,5 +99,5 @@ SLEIGH & P-Code References -------------------------- Extensive documentation covering SLEIGH and P-Code is available online: -* `SLEIGH, P-Code Introduction `_ -* `P-Code Reference Manual `_ \ No newline at end of file +* `SLEIGH, P-Code Introduction `_ +* `P-Code Reference Manual `_ \ No newline at end of file diff --git a/docs/index.rst b/docs/index.rst index dd5ae38..d7ff7dc 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -1,7 +1,7 @@ pypcode documentation ===================== pypcode is a machine code disassembly and IR translation library for Python using the -excellent `SLEIGH `__ library from the `Ghidra `__ framework (version 12.0.1). +excellent `SLEIGH `__ library from the `Ghidra `__ framework (version 12.0.2). This library was created primarily for use with `angr `__, which provides analyses and symbolic execution of p-code. diff --git a/pypcode/processors/AARCH64/data/languages/AARCH64base.sinc b/pypcode/processors/AARCH64/data/languages/AARCH64base.sinc index e07d50a..35ada38 100644 --- a/pypcode/processors/AARCH64/data/languages/AARCH64base.sinc +++ b/pypcode/processors/AARCH64/data/languages/AARCH64base.sinc @@ -2698,7 +2698,7 @@ is b_3031=0b10 & b_2129=0b111000101 & b_1015=0b110000 & Rn_GPR64xsp & aa_Wt & ls # size == 11 64-bit variant :ldapr aa_Xt, [Rn_GPR64xsp] -is b_3031=0b11 & b_2129=0b111000101 & b_1015=0b110000 & Rn_GPR64xsp & aa_Xt +is b_3031=0b11 & b_2129=0b111000101 & b_1015=0b110000 & Rn_GPR64xsp & aa_Xt & ls_data8 { aa_Xt = tmp_ldXn; } diff --git a/pypcode/processors/ARM/data/languages/ARMinstructions.sinc b/pypcode/processors/ARM/data/languages/ARMinstructions.sinc index 4eba7c1..0fc0d9b 100644 --- a/pypcode/processors/ARM/data/languages/ARMinstructions.sinc +++ b/pypcode/processors/ARM/data/languages/ARMinstructions.sinc @@ -2868,9 +2868,10 @@ ArmPCRelImmed12: reloff is U23=0 & immed & rotate :ldrexd^COND Rd,Rd2,[Rn] is $(AMODE) & ARMcond=1 & COND & c2027=0x1b & Rn & Rd & Rd2 & c0011=0xf9f { - build COND; - Rd = *(Rn); - Rd2 = *(Rn + 4); + build COND; + local addr:4 = Rn; + Rd = *(addr); + Rd2 = *(addr + 4); } :ldrexh^COND Rd,[Rn] is $(AMODE) & ARMcond=1 & COND & c2027=0x1f & Rn & Rd & c0011=0xf9f diff --git a/pypcode/processors/PowerPC/data/languages/ppc_vle.sinc b/pypcode/processors/PowerPC/data/languages/ppc_vle.sinc index 7b08e4b..9e6f83e 100644 --- a/pypcode/processors/PowerPC/data/languages/ppc_vle.sinc +++ b/pypcode/processors/PowerPC/data/languages/ppc_vle.sinc @@ -114,7 +114,7 @@ IMM16B: val is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) | :se_blrl is $(ISVLE) & OP15_VLE=2 & LK0_VLE=1 { tmp:$(REGISTER_SIZE) = LR & ~1; LR = inst_next; - return [tmp]; + call [tmp]; } :se_sc is $(ISVLE) & OP16_VLE=2 { diff --git a/scripts/sleigh_download.sh b/scripts/sleigh_download.sh index ef93684..0832098 100755 --- a/scripts/sleigh_download.sh +++ b/scripts/sleigh_download.sh @@ -2,7 +2,7 @@ set -e set -x -TAG=12.0.1 +TAG=12.0.2 GHIDRA_SRC_DIR=ghidra_src_${TAG} git clone --depth=1 -b Ghidra_${TAG}_build https://github.com/NationalSecurityAgency/ghidra.git ${GHIDRA_SRC_DIR}